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Abstract: An approximate expression for the thermal resistance of a bolted microelectronic chip carrier is developed by using a novel analytical approach for treating mixed boundary conditions. Results obtained for the thermal resistance indicate that there is an optimum thickness to minimize the resistance. Lift-off of the outer edge of the carrier has a negligible effect on the resistance for carriers fabricated with the optimum thickness. By increasing the amount of lift-off for carriers with a thicknesses less than the optimum value, there is often a reduction in the thermal resistance. For carriers with thicknesses above the optimum value, an increased amount of lift-off causes the resistance to rise.
22nd Thermophysics Conference, June 8-10, Honolulu, HI (AIAA Paper No.87-1613)
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